In the design of integrated circuits containing memory, a certain mount of redundancy is built in so that defects arising during manufacturing of the integrated circuit can be cured by replacing the defective element with a redundant element. The process of replacing the defective elements with redundant elements is referred to as "mapping" whereby the defective element is "mapped out" and the redundant element is "mapped in." Mapping is typically performed by fuse logic circuitry that is controlled by one or more programmable fuse circuits which are programmed to output a logic control signal to the fuse logic circuitry. A programmable fuse circuit is usually programmed by either blowing or not blowing a fuse associated with the programmable fuse circuit.
As an example, a memory bank comprising a plurality of memory elements is a regular structure that is well suited for designing in redundancy, i.e., redundant memory elements. If during manufacturing one of the memory elements in the bank is defective, then the fuse logic circuitry associated with the memory bank can be programmed to map out the defective element and to map in a redundant element. Accordingly, in order to know which memory elements are defective, integrated circuit manufacturers perform various types of test at various points in the manufacturing process. Of particular relevance with regard to the present invention is one such test referred to as a wafer test.
In general, wafer testing is a means of verifying correct operation of an integrated circuit once manufactured and in wafer form.
Thus, once the integrated circuit has been manufactured but before the wafer is cut into individual dies, wafer tests are performed on the integrated circuit in order to determine if the memory is operating properly or if there are defective memory elements therein. If any defective memory elements are located, then the wafer is removed from the wafer tester and is taken to a laser programming station where the programmable fuse circuits are programmed to provide the fuse logic circuitry with an appropriate logic pattern for mapping the memory bank. The programmable fuse circuits are programmed at the laser programming station by a laser that "blows" the fuses associated with selected programmable fuse circuits. Currently, there are no means available for verifying that the laser programming is successful without performing a second wafer test. Therefore, the wafer is then returned to the wafer tester for retesting the integrated circuit in order to confirm the laser programming fixed the defect prior to the final assembly of the integrated circuit. The foregoing process is not only costly and time consuming, but it also requires the integrated circuit to be wafer tested twice, and thereby, increasing the possibility of further damaging the integrated circuit each time the integrated circuit is handled or tested.
Further, memory banks are often a part of an embedded memory circuit, whereby other circuitry in the integrated circuit uses (i.e., depends on) the embedded memory. Consequently, the memory must be fully functionally and configured in its final state in order for complete testing of the other non-memory circuits. If the operation of the memory is not fully configured at the first wafer test, then the other circuits that use the memory cannot be fully tested until the memory has been mapped and second wafer test performed to confirm the fix. Again, this is costly and time consuming.
Another option is to test the memory and the non-memory circuits independently at wafer test, configure the redundant elements of the memory, and then test the final assembly in package form. However, this leaves the interface between the memory and non-memory circuits untested, and therefore, defects may exist that cause the integrated circuit to fail final testing. Thus, the cost of assembling and packaging the integrated circuit is lost if the integrated circuit fails final testing. Another disadvantage to this option is that the non-memory circuits may be impossible to test without the memory being configured. This may cause additional yield loss at final testing.
In addition, once an integrated circuit has been packaged and placed in use, certain physical phenomenons and/or activities may contribute to latent defects. When such defects occur, the integrated circuit is typically viewed as irreparable, and therefore, the integrated circuit (or the product within which it is packaged) must be replaced. Currently, there are no means available for reprogramming the programmable fuse circuits that control the fuse logic circuitry in order to overcome latent defects.
Accordingly, a heretofore unaddressed need exists in industry for a system and method for controlling the output of programmable fuse circuits so as to be able to reprogram the programmable fuse circuits without having to permanently program the programmable fuse circuits.